1. Field of the Invention
The present invention relates to a design aiding apparatus and a method for the design of semiconductor devices. To be more precise, the present invention relates to a reliability verifying tool and process serving as a design aiding apparatus and method for designing of semiconductor devices. In addition, the present invention also relates to a logic-circuit synthesizing tool and a process useful in the design of semiconductor devices. Similarly, the present invention relates to an automatic layout/wiring tool and process useful in the design of semiconductor devices.
2. Discussion of the Related Art
In recent years, a method for determining degradation caused by hot carriers in a MOS transistors forming a semiconductor device has been used in which hot carrier dependent lifetime of each transistor is calculated from real wave form data of inputs and outputs obtained from a known SPICE circuit simulation. Any transistor with a lifetime shorter than a predetermined reference value is determined to be a defective transistor.
Since this method uses a SPICE circuit simulation, it takes a very long simulation time to determine the defective transistors in a circuit of large scale with many such transistors. Further, a memory with a large storage capacity is required for storing wave form data of nodes of transistors for such a circuit.
Further, with conventional design aiding tools for providing semiconductor devices, such as a logic-circuit synthesizing tool or an automatic layout/wiring tool, the operational speed of a circuit being provided can be optimized, but the reliability of component transistors in terms of hot carrier degradation or the like is not taken into consideration, so that the circuit being provided may have poor reliability.